The present invention relates to designing a timing closure of integrated circuits.
With the advent of deep submicron technologies, the dominance of integrated circuit performance has shifted from logic to interconnect. Therefore, designers have shifted the design paradigm from a conventional logic-dominated design process to an interconnect-dominated design process. The interconnect-dominated design process can be implemented by applying timing closure of practices of integrated circuits from prototyping through tape out.
One fundamental problem with timing closure of integrated circuits in the early stages is modeling top level interconnect delay. The top level interconnect are wires connecting the functional units and IOs together. Years ago each top level interconnect was considered zero delay. Below one micron, this delay had to be estimated, usually with some custom wire loads. Today, the delay must be more accurate. One could route the top level design, and perform static timing analysis (STA), but the slew degradation caused by very long wires would be unrealistic.
A common practice is merely to give some percentage of the clock to the top level interconnect. However, in some cases this will be too pessimistic and in other cases too optimistic.
Several methods have been conventionally used for minimizing interconnect delay for designing the timing closure of the integrated circuits. One such method includes insertion of repeaters, based on a buffer rule file. This buffer rule file defines, for various sizes of buffers/inverters, a length and capacitance, i.e., for a certain size buffer/inverter it could drive say 100 microns or 5 pF (picofarads). However, this method involves instantiating largest buffers, because the algorithm wants to insert the fewest repeaters. Thus, if there is a long wire, the biggest repeaters are considered first, then the next biggest, so on and so forth down to the smallest repeater. As a result, the method requires more space, consumes more power, and causes congestion.
In light of the foregoing discussion, a need exists for a manner for designing an early timing closure of integrated circuits. The present invention addresses such a need.